1. Field of the Invention
The present invention generally relates to a frequency synthesizer and more particularly to an improved circuit for controlling loop dynamics of the frequency synthesizer.
2. Description of the Related Art
Conventional systems utilize frequency synthesizers for a wide range of purposes. For example, frequency synthesizers are used in computer storage systems (such as optical, magnetic, and the like). In order to record digital data onto the surface of a storage medium, which is typically in the form of a rotating magnetic or optical disk, surface characteristics of the disk are modified. Digital data modulates the operation of a write transducer (write head) which records binary sequences onto the disk in radially concentric or spiral tracks. In magnetic recording systems, for example, the digital data modulates the current in a write coil in order to record a series of magnetic flux transitions onto the surface of a magnetizable disk. And in optical recording systems, for example, the digital data may modulate the intensity of a laser beam in order to record a series of xe2x80x9cpitsxe2x80x9d onto the surface of an optical disk. When writing this recorded data, a write transducer (write head), positioned in close proximity to the rotating disk, generates a sequence of corresponding pulses in an analog write signal.
The frequency synthesizer is used to code the pulses into a digital sequence. Discrete-time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete-time sequence detectors increase the capacity and reliability of the storage system.
A phase-locked-loop (PLL) frequency synthesizer normally implements the timing recovery decision-directed feedback system. The PLL comprises a phase detector for generating a phase error estimate based on the difference between the estimated samples and the write signal samples. A PLL loop filter filters the phase error, and the filtered phase error operates to synchronize the channel samples to the baud rate. Conventionally, the phase error adjusts the frequency of a sampling clock which is typically the output of a variable frequency oscillator (VFO). The output of the VFO controls a sampling device, such as an analog-to-digital (A/D) converter, to synchronize the sampling to the baud rate.
However, the loop dynamics of conventional frequency synthesizers is controlled using external components, which increases the size of the frequency synthesizer and decreases performance. Driving these external components requires increased power to overcome parasitic loading due to package and card wiring. This requires higher operating power.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional frequency synthesizers, the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved frequency synthesizer.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, a frequency synthesizer that includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit.
The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.
With the invention, the fractional integration counter will allow raising the charge pump current and provide fixed acquisition and tracking current corrections so as to provide sufficient signal to noise ratio, while achieving a lower effective integration current. The fractional integration counter allows the user to adjusts loop dynamics by simply adjusting the FI (fractional integration) value. The proportional multiplier, when used with the fractional integration counter can adjust loop bandwidth and maintain damping or vice versa.